PLLMUL=others, PLODIV=00
PLL Clock Control Register2
| PLLMUL | PLL Frequency Multiplication Factor Select 0 (others): x PLLMUL[4:0] +1 15 (1111): Settings prohibited. |
| Reserved | This bit is read as 0. The write value should be 0. |
| PLODIV | PLL Output Frequency Division Ratio Select 0 (00): /1. 1 (01): /2. 2 (10): /4. 3 (11): Setting prohibited. |